Circuits for charging and discharging a capacitive load are perverse in the art. However, there always seems to be a need for a circuit that will charge and discharge a capacitive load more quickly or with less power than those circuits known in the art. This is especially true when the load is a memory cell of a monolithically integrated memory cell array.
Memory cells are circuits wherein information may be stored in a low current stand-by mode and may be written or read in a higher current mode. A predetermined number of cells are located in a row between each of a plurality of upper and lower word lines and another predetermined number of cells are located in a column between a plurality of bit lines. In other words, each cell is uniquely coupled between a combination of word lines and bit lines.
Conventionally, a row of cells is selected when increased voltage is supplied to the upper word line by a row selection circuit. A particular cell in that row is read by a sense amplifier coupled to the bit lines. A first read current through one bit line flows directly from the sense amplifier. A second read current through the other bit line flows through one side of the memory cell from the upper word line. When a cell is written, the first read current is directed through the cell and the second read current is directed from the sense amplifier.
A stand-by current source is coupled between the lower word line and a second voltage terminal for sinking current from the selected row of memory cells. However, this standby current source provides a very small current in order to minimize total current requirements of the array. Therefore, the time to deselect the cell is very lengthy.
One well known improvement on the above conventional circuit comprises having each lower word line connected to the anode of a diode. A kicker current source is coupled between the cathode of a selected diode and the second voltage terminal. The kicker current source carries a larger current than the stand-by current source, i.e., ten times as large, and provides for a much quicker sink of current from the lower word line. The diode typically comprises a transistor having its base coupled to its collector. However, these diodes create an inherent capacitance, i.e., base-emitter diffusion capacitance, that the kicker current source must discharge in addition to sinking current from the lower word line. While one row is being deselected, another row is being selected. The kicker current source will switch from the cell being deselected to the memory cell being selected as the magnitude of the word line voltages cross, thereby slowing down the deselection process.
Another known improvement is disclosed in "A High Speed 16 kbit ECL RAM", IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-18, No. 5, October 1983. A first transistor is coupled between the lower word line and the kicker current source (in place of the diode of the above described circuit). The base of the first transistor is coupled to a resistor-capacitor (RC) network. A second transistor has its base coupled to the upper word line and supplies current to the RC network. An additional current source is coupled between the RC network of each upper word line and a second supply voltage terminal. The charge from the RC network keeps the first transistor on longer after deselection of the cell, thereby providing a quicker reduction of the voltage of the lower word line. Also, the RC network will keep the first transistor off longer after selection of the cell, providing for a quicker increase of the voltage of the going high lower word line, and also preventing the first transistor from robbing the kicker current from the lower word line being deselected. However, this circuit requires the additional second transistor for each row of cells and the additional current source, thereby consuming valuable space on the array's integrated circuit. Also, the additional current source increases the power requirements of the array significantly. Another known circuit substitutes a diode for the second transistor of the just described circuit and includes a diode coupled between the lower word line and the kicker current source. However, this circuit suffers the same deficiencies of the previously described circuit.
A circuit similar to the present invention, also assigned to Assignee of the present invention, is found in pending Application Ser. No. 815,846, wherein a transient driver circuit for use with a logic circuit has an emitter-follower output stage that sources current to a load connected to an output thereof in response to an applied logic signal being at a first logic level. The transient driver circuit includes a first NPN transistor having a collector-emitter path coupled between the output of the logic circuit and the negative power supply rail. A second NPN transistor has its collector-emitter path couple between a positive power supply rail and the collector of the first NPN transistor and its base adapted to receive the logic signal. Feedback circuitry, that is responsive to a rise in the collector voltage of the second NPN transistor occurring as the logic signal switches to a second logic level, transfers this rising voltage to the base of the first NPN transistor, thereby turning it on harder to sink a large transient current at the output of the logic circuit. This circuit cannot be used as described to charge and discharge a row of memory cells.
Thus, what is needed is an improved bipolar circuit for charging and discharging a capacitive load, i.e., a memory word line selection circuit and word line pulldown circuit that provides either a quicker discharge, or a discharge requiring less power than previously known, of the word line of a row of memory cells.